1. Field of the Invention
The present invention relates to a waveform controller for generating various waveforms for an IC tester.
2. Description of the Related Art
Explanation is presented with reference to the figures regarding the prior art.
Explanation is first presented regarding an embodiment of a semiconductor IC tester described in Japanese Patent Laid-open No. 110357/95 as an example of a prior-art waveform controller for an IC tester.
FIG. 1 is a circuit diagram showing the construction of the prior art, and FIG. 2 is a chart showing the waveform generated by the prior art.
The three edge signals T1-T3 are each outputted at times corresponding to a desired timing edge by a timing generator (not shown). A control signal transmitted from waveform memory (not shown) is supplied to another terminal of AND gate 12 not shown in the figure. The various waveforms for an IC tester are produced by the time settings of signals T1-T3 and the content of waveform memory. Here, waveform memory stores waveform data for forming waveforms.
Signals T1-T3 pass through skew variable regulators 111-113, respectively, and are inputted to AND gates 12S and 12R. The output from the AND gates 12S are transmitted to OR gate 14S through a respective skew regulator 13S. The output from the AND gates 12R are similarly transmitted to OR gate 14R through skew regulators 13R. A set signal is outputted from OR gate 14S, and a reset signal is outputted from OR gate 14R.
Signal T3 is also outputted as signal DREL through skew variable regulator 113, AND gate 123, and skew regulator 133. Signal T4 is outputted as signal DRET through skew variable regulator 114, AND gate 124, and skew regulator 134. Signals T5 and T6 are both used as strobe signals.
In a per-pin tester of the prior art, since waveforms are generated to output three edge signals for set signals and three edge signals for reset signals in each cycle as shown in FIG. 2, as for SBC (Surrounded by Complement) waveforms to a driver, three edge signals T1-T3 of FIG. 1 are split into two to obtain each set and reset signals. As a result, two systems of skew regulators must be provided for one edge signal.
In view of the problem of the prior art, it is an object of the present invention to provide a waveform controller for an IC tester with the purpose of decreasing the number of skew regulators to half or fewer than the number used in the prior art and thus reducing both circuit scale and power consumption.
As a solution to the above-described problem, the present invention provides a waveform controller for an IC tester that includes selectors and OR circuits for inserting strobe-signal edge signals into the driver signal system, and thus allows an edge signal for strobes to be used as a driver signal edge for driver pins.
The present invention allows the number of provided skew regulators to be reduced to half the number or fewer than are used in the prior art by using strobe-signal edge signals as driver waveform edges when using for pins dedicated to the driver, and the invention therefore has the effect of reducing both circuit scale and power consumption.
The above and other objects, features, and advantages of the present invention will become apparent from the following description based on the accompanying drawings which illustrate examples of the present invention.